Engineers talk about FPGA timing constraints seven-step method

From the results of recent work and study, I have summarized the following methods for timing constraints. In the order from easy to difficult:

0. Core frequency constraints

This is the most basic, so the label is 0.

1. Core frequency constraint + timing exception constraint

Timing exception constraints include FalsePath, MulTIcyclePath, MaxDelay, and MinDelay. But this is not the most complete timing constraint. If there are only these constraints, the designer's thinking is limited to the inside of the FPGA chip.

2. Core frequency constraint + timing exception constraint + I / O constraint

I/O constraints include pin assignment location, idle pin drive mode, external trace delay (InputDelay, OutputDelay), pull-up resistor, drive current strength, and more. The timing constraint after adding I/O constraints is the complete timing constraint. As a device on the PCB, the FPGA is part of the timing closure of the entire PCB system. As part of the PCB design, FPGAs require PCB design engineers to read and analyze their I/O TIming Diagram just like all COTS devices. FPGAs differ from COTS devices in that their I/O TIming can be adjusted to a certain extent later in the design; however, it is best to give sufficient consideration and design documentation in the early stages of PCB design. Riple

Because the I/O TIming of the FPGA changes during design, accurately constraining it is an important factor to ensure that the design is stable and controllable. Many of the problems with unstable FPGA operation of external devices after the FPGA is recompiled may be caused by this.

3. Core Frequency Constraint + Timing Exception Constraint + I/O Constraint + Post-fit Netlist

The process of introducing Post-fit Netlist starts with a successful timing closure result, fixing the layout position and routing result (Netlist) of a specific set of logic (Design Partition) on the FPGA to ensure that the layout result can be Reproduce in the new compilation, and accordingly, the timing closure results of this set of logic are guaranteed. The process of retaining the last compilation result in this part is Incremental Compilation. The reserved netlist type and the degree of retention can be set, not limited to Post-fit Netlist, so as to obtain the corresponding retention strength and optimization effect. Thanks to the strong support of EDA tools, although it is a fine-grained constraint to the gate level, the designer only needs to perform a series of setting operations, and does not need to care about the specific information of layout and wiring. Since the content of the constraint to the gate level is too large, it can not be saved in the qsf file, and the retained netlist can be output to a separate file qxp in the form of Partial Netlist, and the coarse configuration information in the qsf file is added together. Compile.

4. Core Frequency Constraint + Timing Exception Constraint + I/O Constraint + LogicLock

LogicLock is a layout constraint at the bottom of the FPGA device. The constraints of LogicLock are coarse-grained and only specify the layout position and size (LogicLock Regions) that the top-level module or sub-module can adjust. A successful LogicLock requires the designer to anticipate possible timing closure goals, consider the impact of the positional relationship of a particular logic resource (pin, memory, DSP) and LogicLock Region on timing, and can refer to the results of the last successful convergence of timing. This trade-off and the process of planning the underlying physical layout of the FPGA is FloorPlanning. LogicLock gives the designer more control over the layout location and scope, effectively passing the designer's design intent to the EDA tool, avoiding EDA tools blindly optimizing non-critical paths due to lack of layout priority information. Since the layout position change of the module in each compilation is limited to the optimal fixed range, the reproducibility of the timing convergence result is higher. Due to its coarse-grained nature, LogicLock does not have a lot of constraint information and can be preserved in the qsf file.

It should be noted that methods 3 and 4 can often be mixed, that is, for the LogicLock Region specified by FloorPlanning, it is used as a Design Partition for Incremental Compilation. This is the reason why the above two methods are easily confused.

5. Core frequency constraints + timing exception constraints + I / O constraints + register layout constraints

Register layout constraints are fine-grained layout constraints that are accurate to the register or LE level. Designers get reliable timing closure results by applying precise control over the design. Manually placing layout constraints on each register in the design and ensuring timing closure is a huge undertaking, marking the designer's ability to fully control the physical implementation of the design. This is an ideal goal and it is impossible to complete it in a limited time. The usual practice is that the designer performs register layout constraints on the design and obtains timing closure information by actually running the place and route tool, and approximates the expected timing target through several iterations. Riple

Not long ago I saw a design like this: every register of a submodule is bound by a specific layout position. The timing closure of the module is correspondingly guaranteed during each recompilation. After analysis, the design and constraints of this sub-module were originally carried out in the schematic diagram. After reaching the timing closure goal, the design was converted to HDL language description, and the corresponding constraints were saved to the configuration file.

6. Core frequency constraint + timing exception constraint + I / O constraint + specific path delay constraint

Good timing constraints should be "guided" and not "mandatory". By giving a range of timing delays for critical paths in the design, leaving the specific work to the EDA tool is freely implemented within the limits of the constraint. This is also an ideal goal. It requires the designer to be aware of each timing path. It is necessary for the designer to distinguish which paths can be converged by the core frequency and simple timing exception constraints. Which paths must be developed by MaxDelay and MinDelay. One, one can not be missed, and also needs the strong support of EDA tools "to understand." Setting the path delay constraint is to set the layout and routing constraints indirectly, but it is more flexible than the methods of 3, 4, and 5 above, without losing its accuracy. Timing closure is the essence of timing constraints through timing constraints rather than explicit layout and netlist constraints.

I remember that some netizens said that "good timing is designed, not constrained." I have always used this sentence as my own guidance for logic design and timing constraints. Good constraints must be based on good design. Without a good design, it doesn't make sense to work harder and harder. However, the correctness and inferiority of the design can also be checked by the correct constraints. The timing analysis report can be used to check the timing of the design. Through several iterations of “analysis-modification-analysis”, the goal of perfecting the design can also be achieved. It should be said that design is the basis of constraints, constraints are the guarantee of design, and the two are complementary.