Xilinx FPGA User Constraint File

There are three types of constraint files in FPGA design: user design files (.UCF files), netlist constraint files (.NCF files), and physical constraint files (.PCF files), which can complete timing constraints, pin constraints, and region constraints. The relationship between the three types of constraint files is: the user writes the UCF file in the design input stage, then the UCF file and the design are combined to generate the NCF file, and finally the PCF file is generated after the implementation. The UCF file is an ASC 2 code file that describes the constraints of the logic design and can be edited with a text editor and a Xilinx constraint file editor. The syntax of the NCF constraint file is the same as that of the UCF file. The difference between the two is: UCF file is input by the user, and the NCF file is automatically generated by the synthesis tool. When there is a conflict between the two, the UCF file is taken as the priority of the UCF. highest. The PCF file can be divided into two parts: one is the physical constraint generated by the mapping, and the other is the constraint input by the user. Similarly, the user-constrained input has the highest priority. In general, user constraints should be completed in the UCF file. It is not recommended to directly modify the NCF file and PCF file.
The constraint file has a .ucf suffix, so it is also commonly referred to as a UCF file. There are two ways to create a constraint file, one is through the new method, and the other is done using the process manager.

The first method: create a new source file, select "ImplementaTIon Constrains File" in the code type, and enter the name of the constraint file in "File Name". Click the "Next" button to enter the module selection dialog box, select the module to be constrained, then click "Next" to go to the next page, and then click the "Finish" button to complete the creation of the constraint file.
The second method: In the project management area, set "Source for" to "Synthesis/ImplementaTIon". The “Constrains Editor” is a dedicated constraint file editor. You can open the “Constrains Editor” by double-clicking “Create TIming Constrains” under “User Constrains” in the process management area.
It should be noted that the UCF file is size sensitive, the port name must be the same as the name in the source code, and the port name cannot be the same as the keyword. But the keyword NET is not case sensitive.
The syntax of the UCF file:
1. grammar
The syntax of the UCF file is:
{NET|INST|PIN} "signal_name" Attribute;
Where "signal_name" refers to the name of the object being constrained, including the description of the level of the object; "Attribute" is a specific description of the constraint; the statement must end with a semicolon ";". You can add comments with "#" or "". It should be noted that UCF files are case sensitive, and the signal names must be the same as the case in the design, but the keywords of the constraints can be uppercase, lowercase, or even mixed case. E.g:
NET "CLK" LOC = P30;
“CLK” is the constrained signal name, LOC = P30; it is the specific meaning of the constraint, and the CLK signal is assigned to the P30 pin of the FPGA.
For all constraint files, using the same signal name as the constraint keyword or design environment reserved word will generate an error message unless it is enclosed in "", so when entering the constraint file, it is best to use " " to signal all signals Name the name. 2. Wildcards In UCF files, wildcards refer to "*" and "?". "*" can represent any string as well as empty, and "?" represents a character. When editing a constraint file, you can use a wildcard to quickly select a set of signals, all of which contain a partially shared string. E.g:
All signals that contain the "CLK" character and end with one character and increase its rate.
In position constraints, you can use wildcard characters in line numbers and column numbers. E.g:
INST "/CLK_logic traverses level1 modules, but does not traverse lower-level module pins and region constraint syntax (can also be constrained by Floorplanner)
The LOC constraint is the most basic layout constraint and comprehensive constraint in FPGA design. It can define the position of the basic design unit in the FPGA chip, and can achieve absolute positioning, range positioning and regional positioning. In addition, the LOC can constrain a set of basic units in a specific area. The LOC statement can either be written in the constraint file or added directly to the design file. In other words, the main functions of the FPGA underlying FPGA Editor, Floorplanner, and Pin and Region Constraint Editor in ISE can be done through LOC statements.
LOC statement syntax
INST "instance_name " LOC = locaTIon;
Where "location" can be any one or more legal locations in the FPGA chip. If there are multiple locations, they need to be separated by a comma "," as follows:
LOC = location1, location2,...,locationx;
Currently, it is not yet supported to place multiple logics in the same location and multiple logics in multiple locations. It should be noted that the multi-position constraint does not locate the design at all locations, but in the place-and-route process, the layouter arbitrarily selects one of them as the final layout position. The syntax for range targeting is:
INST "instance_name" LOC=location:location [SOFT];
Table commonly used LOC positioning statement Common LOC positioning statement

When using LOC to complete a port definition, the syntax is as follows:
NET "Top_Module_PORT" LOC = "Chip_Port";
Among them, "Top_Module_PORT" is the signal port of the top-level module in the user design, and "Chip_Port" is the pin name of the FPGA chip.
There is a priority in the LOC statement. When the LOC port and its port are simultaneously connected, the priority of the connection constraint is the highest.

2. LOC attribute description

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