Analysis of communication structure of dynamic reconfigurable system

Analysis of communication structure of dynamic reconfigurable system

Driven by certain control logic, the dynamic reconfigurable technology can realize the dynamic function transformation of the system and the time-division multiplexing of the hardware for all or part of the logic resources. This paper introduces the reconfigurable architecture and typical dynamic reconfigurable architecture; analyzes and compares the main performances of the four communication architectures of the dynamic reconfigurable system in detail, points out their respective applicable fields, and gives an application example; finally, the dynamic Relevant problems and development trends facing research on reconfigurable technology.

Keywords Reconfigurable Dynamic Reconstruction NoC RPU

The advent of SRAM-based FPGAs marked the beginning of modern reconfigurable computing technology and greatly promoted its development. Reconfigurable computing technology can provide the efficiency of hardware and the programmability of software. It combines the characteristics of microprocessors and ASICs. The spatial and temporal dimensions are both variable. Therefore, it is widely used in military target matching, large number operations, and acoustics. Nanobeam synthesis, genome matching, image texture filling, computer-aided design of integrated circuits, etc. The research on dynamic reconfigurable technology will promote the development of reconfigurable technology to meet more application requirements.

1 Reconfigurable architecture

Figure 1 Coupling relationship between the reconfigurable unit RPU and the traditional microprocessor

The basic architecture constructed with reconfigurable devices can be divided into the following four types according to the coupling method of the reconfigurable processing unit RPU and the traditional microprocessor:

â‘  As a separate processing unit connected to the bus through the I / O interface, it is the most loose connection method, as shown in Figure 1 (a);
â‘¡ The processing unit as the main processor is hung on the local bus of the host, and the connection between the main processor and the main processor is achieved through Cache, as shown in Figure 1 (b);
â‘¢ As a co-processing unit, it can perform larger-granularity operations, as shown in Figure 1 (c);
â‘£ The RPU is integrated into the processor chip as an extended data channel of the main processor, providing instructions whose functions can be customized, as shown in Figure 1 (d).

2 Typical dynamic reconfigurable system structure

Reconstruction can be divided into static reconstruction and dynamic reconstruction. If the reconstruction must be run with interrupted program execution, it is called "static reconstruction"; if the process of loading the configuration file can be performed simultaneously with the program execution, that is, while changing the circuit function, the dynamic connection of the circuit is still guaranteed It is called "dynamic reconstruction". Dynamically reconfigurable systems are mostly based on RPU with multiple configuration files, which can change other configuration files while running some configuration files, thus significantly reducing the time for reconfiguration. Dynamic reconfigurable technology can make the single-chip design of digital systems shift from the pursuit of large-scale logic and high integration to the pursuit of resource utilization, from a dedicated fixed-function logic system to a logical system with adaptive evolution of functions. Its design theory and The method has gradually become a new research hotspot. The following introduces several typical dynamic reconfigurable structures.

Garp: A system composed of a MIPS microprocessor and FPGA developed by the BRASS research team at the University of California, Berkeley. Its core is to explore how to embed the reconfigurable computing unit into the traditional RISC processor, and demonstrate the variable structure's ability to accelerate the calculation of certain fields.

M1, M2 chip: M1 chip is a coarse-grained, multiple configuration file reconfigurable structure proposed by the University of California Morphosys project; M2 is an improved structure of M1, which combines the flexibility of DSP devices and the high performance of ASIC chips , Can be widely used in parallel computing systems, multimedia data processing, high-quality image processing, DSP transformation and other fields.

FIPSOC: A coarse-grained FPGA proposed by SIDNA Engineering. The sequential logic part has the dynamic reconstruction function of multiple configuration files. To support dynamic reconstruction, the data in each register can be copied, and the instructions and functional units of the microprocessor have been improved.

DPGA: proposed by the Transit project of the Massachusetts Institute of Technology, divided into two-dimensional array of DRFPGA. When the DPGA device realizes the time reconfiguration, the AE needs to be able to implement multiple functions for configuration, while the conventional FPGA only implements the repeated configuration of the same function.

XPP (eXtreme Processing Platform) structure: A coarse-grained real-time dynamic reconfigurable data processing technology proposed by PACT company. Its central idea is to replace the instruction stream with a configuration stream to support parallel tasks. XPP is very efficient for processing large amounts of streaming data, and is suitable for wireless base stations, images, video stream processing, radar sonar, biological information, process simulation, and encryption.

3 Communication structure of dynamic reconfigurable system

3.1 Two basic strategies

Typical system-on-chip designs often use two communication strategies: on-chip bus and on-chip network. The most commonly used is the on-chip bus. Its main advantages are high flexibility, scalability, and low design costs. Generally, the delay is also shorter when the bandwidth requirements are low; the disadvantage is that too long communication lines bring certain energy consumption and limit System clock rate. When the communication structure contains more than two modules, the scalability is reduced. The layered bus structure can reduce the bus load on the critical path. Connecting multiple buses through a bridge can isolate devices with different speed requirements in different clock domains, allowing the SoC to continue the excellent performance of the PCB board.

Network on chip (NoC) technology completely solves the three major problems inherent in the bus structure: the scalability problem caused by the limited address space; the communication efficiency problem caused by the time-sharing communication; the global synchronization Power consumption and area issues. Its main advantage is that it can support concurrent communication between hardware modules, which is more scalable and can be used to support larger bandwidths, but with longer delays. The modularity of the components is more conducive to IP reuse, thereby providing higher clock frequency and low power consumption. Relative to the bus structure using central control logic, each switching node of NoC contains cache, routing logic, and arbitration logic, so its biggest disadvantage is that the on-chip area costs more.

NoC's topological structure includes direct network Orthogonal topology, cubic connection loop topology, Octagon topology, etc .; indirect network topology Crossbar Switch structure, FullyConnected network and Butterfly topology. The choice of NoC topology will significantly affect the transmission capacity of the communication architecture. In order to match the complexity and cost of the chip architecture, the processing characteristics and application goals of the chip itself, the average distance of the path, the scalable size, the number of nodes, the number of vertices, and the network diameter of the topology must be considered in the communication architecture. Because NoC's topology selection has a decisive influence on the final cost performance of its products, choosing the correct topology can effectively shorten the design and verification time of various applications.

3.2 Communication structure

3.2.1 Classification

Communication structures based on on-chip bus strategy are: RMBoC (Reconfigurable MulTIple Bus on Chip) and BUSCOM. The communication structures based on the on-chip network strategy are: DyNoC (Dynamic Network on Chip) and CoNoChi (Configurable Network on Chip).

RMBoC is proposed for multi-processor systems, based on the improvement of reconfigurable multi-bus network. Any system-level reconfiguration will not change the RMBoC module and physical topology. The communication structure on the application layer changes through a point-to-point channel on the cascading network. This structure has high flexibility, but the scalability is weak, and its structure is shown in Figure 2.

DyNoC is the first structure that uses a packet-based NoC scheme for reconfigurable design. It consists of a two-dimensional array of processing units and routers. Each processing unit is connected to a router, and the routers are connected to each other. The structure's scalability, extensibility and modularity are all very good, but the flexibility is not good. A 5 × 5 DyNoC system structure diagram is shown in Figure 3.

Figure 2 RMBoC structure diagram

Figure 3 5 × 5 DyNoC system structure diagram

The design parameters of the four structures are shown in Table 1, and the execution parameters (experimentally obtained on VirtexII) are shown in Table 2. In particular, the execution parameters of the on-chip bus are for the entire structure, while the execution parameters of the on-chip network are for a single switching node.

These four structures can meet the design requirements of dynamic reconfigurable FPGA well. The structure of the on-chip network reflects better structural parameters, but the on-chip area is costly, so when the design focuses on on-chip efficiency, the on-chip bus structure is preferred.

In addition, BUSCOM requires very little hardware resources, and the flexibility of RMBoC is better than BUSCOM in the layered bus structure; CoNoChi has the best structural parameters and is the most theoretically dynamic reconfigurable structure, but on the VirtexII The implementation is difficult, so DyNoC is designed to adapt to the limited reconfigurable capabilities of the VirtexII platform.

3.2.2 Application Examples of DyNoC

Traffic light control (TLC) can be realized with a 3 × 3 DyNoC, which is composed of 3 modules: VGA controller (VGA), traffic light vision module (LV) and traffic light control module (TC). The VGA module can display the current intersection situation, pedestrian control keys and light signals; the traffic light vision module is responsible for controlling the internal structure of the traffic light and displayed by the VGA module; the traffic light control module (TC) is used to obtain pedestrian needs. VGA sends X and Y pixel scanning position to the traffic light vision module, and receives the color to be displayed; FSM module is used to monitor the pedestrian's keying input (there are two buttons on the chip), and send the status of the transition light to the traffic light vision module Information, and then display the corresponding color lights. In 3 × 3 DyNoC, the router in the middle is used to connect with all other routers, and other routers also maintain mutual communication to ensure high traffic. The entire traffic light control (TLC) implementation can be run without interruptions and failures.

Table 1 Design parameters of 4 kinds of structures

Table 2 Execution parameters (experimentally obtained on VirtexII)

4 Related issues and development trends

â‘  At present, each IP component in the system-on-chip design can be reused, but the communication structure cannot be reused. Therefore, during system reconstruction, how to provide a flexible and fast communication interface for dynamically configured modules becomes the main problem. It can study a dynamically reconfigurable NoC architecture, which can provide a flexible interface for communication between IPs, and can exchange data with other chips of the board-level system through on-chip pins to provide better communication quality QoS, Including high throughput and short delay.
â‘¡ An important issue in NoC design is to determine the type of routing, which has an important impact on the performance and power consumption of the network. The more complex the routing strategy, the larger the design area, so there is a trade-off between area and performance. The choice of routing strategy should mainly consider the two major issues of implementation complexity and performance requirements.
â‘¢ Reconstructed time slots will affect the continuity of system functions. In order to improve the performance of dynamic reconfigurable computing systems, how to avoid or reduce the reconfiguration time slots is the bottleneck of implementing dynamic reconfiguration systems. For DRFPGA with multiple context structures, the configuration information is changed directly by switching between contexts, and the array unit is controlled to realize the reconstruction of new functions. The switching speed directly affects the length of the reconstruction time, generally only a few ns. The realization of this reconstruction method is the main symbol of the development of dynamic reconstruction technology.

Conclusion

This paper introduces the reconfigurable architecture and the typical dynamic reconfigurable computing structure; it analyzes the communication structure of the dynamic reconfigurable system in detail, and conducts experiments on the main performance of the four communication structures to obtain comparative data; An example of the application of this structure in traffic light control; finally, the related problems and development trends faced by the research of dynamic reconfigurable technology are discussed.