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Power is the top challenge in designing 7nm chips, and extending battery life has become a key competitive advantage. The most effective way to address power issues is by accurately predicting power consumption, identifying where it's being used, and enhancing the coverage of power noise and cooling solutions through real-time power distribution.
Traditionally, chip design focused on performance, power, and area. Moore’s Law pushed for smaller sizes, while microprocessor speed and capability kept increasing. With the rise of smartphones and other mobile devices, power consumption has become a central concern in chip and system design. The emergence of drones, IoT, robots, and wearables—many of which are battery-powered—has accelerated the development of ultra-low-power chips.
Although Moore’s Law is facing challenges, it continues to evolve. Chip manufacturers are exploring new materials like compound semiconductors and 2D materials, while innovations in lithography and 3D transistor structures have introduced new process nodes. The development cycle has extended from 1.5–2 years to 3.5–4 years. However, the main challenge remains power, heat, and noise. As nodes get smaller, insulation layers thin, reducing RC delay but also lowering noise tolerance. Precise power control is essential to prevent overheating and ensure reliability and longevity.
Oliver King, CTO at Moortec, notes that while new nodes offer benefits, balancing power and performance is more complex due to immature processes. For devices expected to last over 10 years, power efficiency becomes even more critical, as a single battery must support the entire lifespan. New architectures, advanced biasing techniques, and innovative design tools are necessary. FD-SOI technology can significantly cut power use, but for smaller designers, the cost and risk of switching from FinFET to FD-SOI remain high.
Battery-powered products are constantly adding features while maintaining or improving battery life, driving demand for better power management, especially in compute-heavy applications like AI and machine learning. Wireless technologies such as ultra-low-power Wi-Fi and 5G modems further emphasize the need for efficient power usage. While power, performance, and size remain core design factors, the balance between them is shifting.
Data centers have long prioritized power efficiency. Server racks, storage systems, and cooling mechanisms all consume energy, and optimizing this is crucial for energy efficiency. As data volumes grow, moving everything to the cloud becomes less efficient, prompting new thinking about local processing and edge computing.
Rainer Herberholz from ARM highlights that ultra-low power is vital for IoT edge systems. Local computing aims to minimize sensor power, reduce cloud communication costs, and increase autonomy. Lowering voltage is an effective strategy, but it comes with challenges, particularly in managing timing variations and ensuring SRAM works reliably at low voltages.
The ARM ecosystem plays a key role in achieving ultra-low power goals, from foundries offering specialized processes to EDA tools that help manage low-voltage design challenges. New cores, IP, and SoC integration methods, whether at the system or software level, all contribute to power reduction.
Preeti Gupta from ANSYS emphasizes that power behavior depends heavily on chip activity. Visualizing power and thermal distribution during early stages—such as when booting an OS—can help identify and resolve issues before they become costly. RTL simulation is a valuable tool for early power and thermal analysis, enabling better design decisions.
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