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**Abstract:**
A GPS Intermediate Frequency (IF) signal acquisition and analysis system has been designed to efficiently capture and process GPS signals. The system utilizes an FPGA to perform serial concatenation of the digital IF signal output from the NJ1006 RF front-end, which is then transmitted to a host computer via USB, enabling high-speed real-time data transfer between the RF front-end and the PC. A custom VC++ application was developed to convert the collected GPS signals into text format and conduct in-depth data analysis. Experimental results confirm that the system successfully acquires GPS IF signals and provides reliable raw data for further research on GPS baseband processing algorithms.
**Keywords:** GPS IF signal; USB; signal acquisition; data analysis
**CLC number:** TN967.1
**Document identification code:** A
**DOI:** 10.16157/j.issn.0258-7998.170792
**Chinese citation format:** Tao Meng, Li Jincheng. Design of a GPS IF signal acquisition and analysis system [J]. Electronic Technology Application, 2017, 43 (9): 34–38.
**English reference format:** Tao Meng, Li Jincheng. Design of a system for sampling and analysis of GPS IF signal [J]. Application of Electronic Technique, 2017, 43 (9): 34–38.
**0 Introduction**
With the widespread use of GPS technology in providing accurate positioning and time information, numerous enterprises and research institutions have focused on the development of navigation and timing chips. This requires detailed analysis of GPS satellite signals. Therefore, developing compact and portable GPS IF signal acquisition equipment is crucial for advancing navigation algorithm research and chip design.
USB interfaces are widely used due to their high data transmission rates and flexible modes, supporting low, full, and high speeds. The highly integrated GPS receiver chip NJ1006 can collect GPS signals in a 2-bit format, and with bit splicing, it can reduce the sampling rate to about 4 MHz, making USB2.0 a suitable choice for data transmission due to its cost-effectiveness and wide adoption.
Based on these considerations, this paper presents a GPS IF signal acquisition and analysis system. It uses an FPGA to perform bit splicing and buffering of the NJ1006 signal, and uploads the data to the PC through a USB2.0 interface chip (FX2-68013). A dedicated VC++ program on the PC side handles data reception, formatting, and analysis.
**1 System Hardware and Software Architecture**
The overall architecture of the GPS IF signal acquisition and analysis system is illustrated in Figure 1. It consists of both hardware and software components. The hardware includes the GPS RF front-end chip NJ1006, an FPGA (Cyclone EP1C12Q240C8N), and a USB2.0 interface chip (FX2-68013). The software comprises a data receiving program, a format conversion program, a data analysis program, and a main control program.
The NJ1006 is a highly integrated GPS RF front-end IC that reduces external components and PCB size by integrating the LNA and local oscillator. It downconverts the 1575.42 MHz GPS L1 signal using a 2-bit ADC, producing a 2-bit digital signal at 16.368 MHz with an intermediate frequency of 4.092 MHz.
The FX2-68013 is a USB2.0 chip from Cypress Semiconductor, featuring an internal 8051 microprocessor that allows configuration in Slave FIFO mode. This setup enables asynchronous data transmission over high-speed channels. The FPGA simulates an I2C memory to avoid interfering with high-speed data flow, allowing the host computer to control the FPGA's operation via I2C.
The FPGA receives the IF signal from NJ1006, performs bit splicing and buffering, sends the data to the USB2.0 chip, and uploads it to the PC. The PC-side software processes the data, converts it, and performs analysis. The primary task involves calculating the two-dimensional correlation value of the C/A code phase and Doppler frequency, visualized in 3D using MATLAB.
**2 FPGA Logic Design**
**2.1 Data Stitching**
The GPS signal is received at 16.368 MHz. Since the signal is 2 bits wide, and the FPGA-to-USB bus is 8 bits, a serial-to-parallel conversion is required. This reduces the write speed to 4.092 MHz, easing timing constraints for data upload.
**2.2 Data Cache**
To ensure real-time data transmission, the FPGA uses its internal M4K memory to create a 26 KB buffer. The data is stored in 13 2 KB RAMs, allowing continuous data flow without interruption. The system cyclically writes and reads data from these RAMs, ensuring stable performance.
**2.3 Data Transfer**
Data is transferred using the FX2’s Slave FIFO mode. Before transmission, the FIFO is configured to 2'b10. The system monitors the FIFO’s status and transfers data when it is not full, creating a high-speed channel for data upload.
**2.4 FPGA State Transition**
The FPGA’s state machine operates at 72 MHz. It initializes the FX2 interface, waits for commands, processes acquisition instructions, and manages RAM read/write operations. When data collection ends, it returns to the waiting state for the next command.
**3 Software Operation**
The upper computer program is written in C++ using MFC, with an intuitive graphical interface. Users can connect via USB, initiate data acquisition, and view results. The software supports ASCII or binary conversion and parameter settings for Doppler frequency, CA code phase, and more. It also enables 3D visualization of correlation results using MATLAB.
**4 GPS IF Signal Acquisition and Analysis Results**
The system was tested at Beijing Jiaotong University on January 13, 2017. The results showed significant correlation peaks around 4.0945 MHz and 16,000 code points. Both absolute and squared summation methods were used, with the former being more resource-efficient. Further refinement of the search range improved accuracy and reliability.
**5 Conclusion**
This paper presents a comprehensive solution for GPS IF signal acquisition and analysis. The USB2.0-based system achieves high-speed and accurate data collection. The time-domain serial acquisition algorithm implemented in C ensures data reliability, laying a solid foundation for future GPS research.