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**Abstract:**
A GPS IF signal acquisition and analysis system has been designed to facilitate the real-time collection and processing of GPS signals. The system employs an FPGA to serially concatenate the digital GPS IF signal from the NJ1006 RF front-end, which is then uploaded to a host computer via USB. This setup enables high-speed data transmission between the RF front-end and the PC. A VC++-based program on the host side handles data conversion and analysis. Experimental results demonstrate that the system not only successfully captures GPS IF signals but also performs detailed data analysis, providing reliable raw data for further research into GPS baseband algorithms.
**Keywords:** GPS IF signal; USB; signal acquisition; data analysis
**CLC number:** TN967.1
**Document identification code:** A
**DOI:** 10.16157/j.issn.0258-7998.170792
**Chinese citation format:** Tao Meng, Li Jincheng. Design of a GPS IF signal acquisition and analysis system [J]. Electronic Technology Application, 2017, 43 (9): 34-38.
**English Reference Format:** Tao Meng, Li Jincheng. Design of a system for sampling and analysis of GPS IF signal [J]. Application of Electronic Technique, 2017, 43 (9): 34-38.
**0 Introduction**
With the increasing use of the GPS global positioning system in providing accurate positioning and time information, many companies and research institutions have focused on developing navigation and timing chips. These functions rely heavily on the analysis of GPS satellite signals. Therefore, the development of compact and portable GPS IF signal acquisition devices is crucial for algorithm research and chip design.
USB interfaces offer high-speed data transfer and flexible communication modes, including low-speed, full-speed, and high-speed transmission, as well as interrupt, control, synchronous, and bulk transfers. This makes them widely used in personal computers. The highly integrated GPS receiver chip NJ1006 can capture GPS satellite signals in 2-bit format, and by bit splicing, it can reduce the sampling rate to about 4 MHz, which is fully supported by USB 2.0. Given its cost-effectiveness and widespread adoption, using USB 2.0 is an optimal choice.
Based on this, the paper presents a GPS IF signal acquisition and analysis system. It uses an FPGA to perform bit splicing and buffering of the NJ1006 signal, and uploads the data to a PC via a USB interface chip (FX2-68013). A custom VC++ program on the PC side is used for receiving, converting, and analyzing the data.
**1 System Hardware and Software Architecture**
The overall architecture of the GPS IF signal acquisition and analysis system is shown in Figure 1. It consists of both hardware and software components. The hardware includes the GPS RF front-end chip NJ1006, an FPGA (Cyclone EP1C12Q240C8N with 20,060 logic units and 52 M4K memory), and a USB 2.0 interface chip (FX2-68013). The software comprises a data reception program, a format conversion program, a data analysis program, and a main control program.
The NJ1006 is a highly integrated RF front-end IC that combines the LNA and local oscillator, reducing the number of external components and PCB area. It downconverts the 1,575.42 MHz GPS L1 signal, samples it using a 2-bit ADC, and outputs a 2-bit digital signal at 16.368 MHz with an intermediate frequency of 4.092 MHz to the FPGA.
The FX2-68013 is a USB 2.0 chip from Cypress Semiconductor that integrates various peripheral interface functions into a single chip. Its internal 8051 microprocessor allows for easy configuration and control. By programming the 8051, the chip can be set to operate in Slave FIFO mode, enabling asynchronous data transfer. Since the chip supports an I2C interface, an FPGA is used to simulate an I2C memory, allowing the host computer to control the FPGA’s operation through I2C.
The FPGA receives the digital IF signal from the NJ1006, performs bit splicing and buffering, sends the data to the USB 2.0 chip, and uploads it to the PC. The PC-side program receives the data, converts it, and performs analysis. The main task involves calculating the two-dimensional correlation value of the C/A code phase and Doppler frequency, and displaying the result in 3D using MATLAB.
**2 FPGA Logic Design**
**2.1 Data Stitching**
The GPS signal is received by the NJ1006 under a 16.368 MHz clock. Since the signal is 2 bits wide and the FPGA-to-USB bus is 8 bits, a serial-to-parallel conversion is needed. This reduces the write speed to 4.092 MHz, easing the timing requirements for data upload.
**2.2 Data Buffering**
Although USB 2.0 offers fast data transfer, the Windows-based PC may not maintain a stable speed due to multitasking. To ensure continuous data flow, the FPGA uses its internal M4K memory to create a 26 KB buffer. The data is temporarily stored in this RAM before being sent via USB 2.0.
The 26 KB buffer is divided into 13 2 KB RAMs. Data is written sequentially into the RAMs, and once filled, the data is read and transferred to the FX2. This cycle ensures real-time data transmission.
**2.3 Data Transfer**
Data is transferred using the FX2’s Slave FIFO mode. Before starting, the Slave FIFO is configured to enable data writing. The system monitors the FIFO’s status and transfers data when it is not full, creating a high-speed channel for uploading data.
**2.4 FPGA State Transition**
The FPGA state machine operates at 72 MHz. It starts in the INIT state, initializes the FX2, and waits for commands. When an acquisition command is received, the system processes it, writes to the RAM, reads the data, and returns to the waiting state after the acquisition is complete.
**3 Software Operation**
The upper-level program is written in C++ MFC, with a graphical user interface. Users can configure the USB connection, issue acquisition commands, and receive data. After acquisition, the data can be converted into ASCII or binary format for easier analysis.
The software also allows users to set parameters such as satellite number, integration time, quantization bits, Doppler frequency range, and CA code phase. By clicking the Analysis button, the system performs a two-dimensional search of the Doppler frequency and displays the results in 3D using MATLAB.
**4 Results of GPS IF Signal Acquisition and Analysis**
The system was tested by collecting and analyzing GPS signals at Beijing Jiaotong University. The results showed a clear correlation peak around 16,000 points and a frequency of approximately 4.0945 MHz. Both absolute and squared summation methods were used, with the absolute method requiring fewer resources.
Further refinement of the search range improved accuracy, and multi-millisecond accumulation helped detect weak signals. These results confirm the system's reliability and effectiveness.
**5 Conclusion**
This paper presents a comprehensive solution for acquiring and analyzing GPS IF signals. The USB 2.0-based data transmission scheme achieves high-speed and accurate signal acquisition. The time-domain serial acquisition algorithm implemented in C language ensures data reliability, laying a solid foundation for future GPS algorithm research.