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Digital amplifiers typically have a two-stage architecture, followed by a power stage at the pulse width modulation (PWM) processor, as shown in Figure 1. The audio data received by the logic-level PWM processor is usually in IIS format. It performs audio processing and converts pulse code modulation (PCM) data into PWM data. The PWM processor is controlled by the IIC bus to perform other audio processing functions such as volume change, tone control or equalization. Another key feature of many PWM processors is the ability to change signal routing (even in real time). This capability gives designers the flexibility to implement PCB layout or give users the ability to send content to different speakers. The power stage receives the 3.3V PWM signal, converts it to a higher voltage, and sends it to the speaker through the MOSFET H-bridge and the second-order LC filter.
The power stage containing the MOSFET H-bridge is shown in Figure 1. Here, the MOSFET acts as a switch to connect the +V voltage to the speaker with positive/negative poles. For most stereo power stages that connect the speaker between two MOSFET half-bridges, the Bridge Load (BTL) is a conventional architecture. Single-ended means that each MOSFET half-bridge drives one speaker. The SE mode has twice the number of channels than the BTL mode, but for a given output load, the power per channel is reduced by approximately 25%. In SE mode, when the PWM signal is "high", the +V voltage is positively applied to the speaker; when the PWM signal is "low", the speaker is grounded.
The operation of a single-ended digital amplifier is shown in Figure 2, which is not much different from the single-ended operation of a linear audio amplifier. The main difference is that the reconstructed filter (second-order LC filter) filters out high frequency components from the PWM signal and preserves the baseband audio signal. Since the speaker impedance has a large inductance component, this is equivalent to passing a high DC voltage through an inductor and increasing the current linearly to a large value, which may cause damage to the speaker.
Figure 1: Digital amplifier data path with H-bridge power stage.
Figure 2: Single-ended digital amplifier with DC blocking capacitor architecture.
To do this, a large capacitor (DC blocking capacitor) can be placed between the amplifier and the speaker to filter out the DC component. However, this capacitor also attenuates the lower audio components and produces a 3dB point of approximately 1/(2Rsp C), where Rsp is the impedance of the speaker. In order to pass higher frequency bands through the speaker, large capacitors can be used, but at the expense of cost and PCB area.
In the single-ended architecture previously discussed, the audio signal is referenced to ground. In other words, one end of the speaker is grounded. Another way to achieve DC blocking is to use a split-cap architecture where the audio signal is referenced to PVDD/2, see Figure 3. From the AC point of view, when Csm = Cb/2, there is no difference between Figure 2 and Figure 3. If a capacitor is inserted, the equivalent series resistance (ESR) of Cs is twice that of Cb, while the audio and thermal performance are unchanged.
Figure 3: Single-ended digital amplifier with split capacitor architecture.
The biggest advantage of the split mode architecture compared to the blocking capacitor architecture is the increased power supply ripple rejection ratio (PSRR). Figure 4 shows the actual measured PSRR of TI's TAS5086/5142 Evaluation Module (EVM). In this EVM, the power level of the TAS5142 is a single-ended architecture.
Figure 4: Single-ended PSRR performance of the TAS5086/5142 EVM.
The SE split mode architecture needs to address two other design issues. As mentioned previously, the audio signal behind the reconstruction filter has a DC component of value PVDD/2. If Cs is ideal, both (Cs and Cb) will be charged to PVDD/2 and no DC component will pass through the speaker. However, since both capacitors are not ideal and have tolerances, the DC voltage will not be equal to PVDD/2. Therefore, when the audio signal is initially applied to the speaker, there will be a DC voltage flowing through the speaker, so squeaking noise will be heard at power up. Since the split capacitor is charged with a fixed time duration of RC, another related problem arises. As long as the MOSFET does not switch before the split capacitor is completed, it will not cause these problems. But in practice it is very difficult to do so, and it will produce long noise.
There is a solution to the above two problems, that is, the voltage can be quickly charged to the half-bridge power stage of PVDD/2, such as TAS5186A. The solution has a 50% duty cycle, the DC voltage output is PVDD/2, and the split capacitor can be charged quickly and accurately. Another way to quickly charge a split capacitor is to use an op amp. The use of an op amp is an effective method when there is no dedicated half bridge.
In practical applications, single-ended amplifier audio performance indicators (including boot noise, signal-to-noise ratio, PSRR and THD+N, etc.) are quite ideal, only slightly worse than BTL's audio performance.