Principles of RF testing behind UMTS testing

This article aims to provide an in-depth understanding of the testing and system principles behind UMTS test projects by analyzing specific test cases. The goal is to help readers grasp the underlying system and testing concepts that drive these procedures. 1. Overview The paper focuses on explaining the testing principles of key RF tests for UMTS terminals, particularly those outlined in the TS34.121 specification. As UMTS evolved from R99 through R5, R6, R7, R8, and R9, the physical layer structure changed significantly. This evolution led to variations in test items across different protocol versions. For example, the maximum power test includes multiple subtests like 5.2, 5.2A, 5.2AA, and 5.2B, each tailored to specific protocol revisions. The complexity of UMTS testing also stems from the latency between various channels and processes. By examining several fundamental UMTS test projects, this article seeks to illustrate the system and testing logic behind them. 1.1. Selection of Trigger Mode In many specifications, you often encounter descriptions such as the following: - "The maximum output power with HS-DPCCH measures the maximum power the UE can transmit when HS-DPCCH is fully or partially transmitted during a DPCCH timeslot." - "The maximum output power with HS-DPCCH and E-DCH measures the maximum power the UE can transmit when HS-DPCCH and E-DCH are fully or partially transmitted during a DPCCH timeslot." These descriptions indicate that the TX test must be conducted when both HS-DPCCH and E-DCH are active. As shown in Figure 4.1, these channels have discontinuous transmission characteristics, so the test should be performed during their activation periods. This ensures the radio performance under active channel conditions is properly validated. According to Figure 1.1, the time difference between the uplink HS-DPCCH and DPCH is m*256 chips, referred to as T1. Here, m = (TTX_diff / 256) + 101, and the delay is approximately 1024 chips in the CMU 200. The delay between uplink DPCH and downlink DPCH is the air interface delay, denoted as T2. The delay between downlink DPCH and CPICH is T3, measured in 256 chips and configurable in both CMU 200 and CMW500. Thus, the total delay between uplink HS-DPCCH and CPICH is T1 + T2 + T3. The comprehensive tester identifies the uplink HS-DPCCH channel based on the downlink frame boundary, CPICH timing, and other system parameters. Once the first HS-DPCCH is located, its periodicity of 12 ms allows the actual occurrence time to be calculated precisely. In practice, the HS-DPCCH trigger can be directly selected in the tester. The principle of E-DCH is similar to HSDPA and will not be detailed here. 1.2. Dynamic Terminal Power Test In LTE systems, certain factors can cause fluctuations in terminal power, such as changes in TFC (including DTX), power boosting in compressed mode, PRACH access in open-loop power control, and TPC response in closed-loop power control. Channel gain factor variations can also affect power levels. To address these power changes, the 3GPP TS34.121 specification defines a response test item, as shown in Table 1.1.

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