Interleaved PFC control technology and application to improve power conversion efficiency - News - Global IC Trade Starts Here 工业

A variety of innovative power factor correction (PFC) technologies have been introduced over the years. Active power factor correction with a boost topology is one of the first innovations. Active power factor correction technology increases power density since large volume passive PFC solutions are no longer needed. Another innovative technology is the transfer mode PFC, which eliminates the reverse recovery current in the boost diode of the PFC pre-regulator, which not only reduces the switching losses of the converter, but also increases system efficiency. The next innovation in PFC to increase power density and increase system efficiency is the interleaved PFC pre-regulator.

Power supply design engineers have designed interleaved PFC converters for several years, but due to the lack of a suitable controller, the design of power control must be very cautious. To make interleaved PFC design easier, Texas Instruments has developed two interleaved PFC controllers: one for the average current mode pre-regulator (UCC28070) and the other for interlaced Transfer mode PFC pre-regulator controller (UCC28060). This article will discuss how to use interleaved PFC and its control techniques to increase power density, increase system efficiency, and reduce system cost.

The interleaved PFC boost pre-regulator (Figure 1) consists of only two PFC boost converters that operate 180° out of phase to reduce the input caused by the inductor currents (IL1 and IL2) Current (IIN). Since the inductor high-frequency ripple current is inverted, the two cancel each other out, thereby reducing the input ripple current caused by the boost inductor current. Elimination of the inductor ripple current allows the power supply designer to parallel boost the PFC pre-regulator while reducing the input ripple caused by the boost inductor, which can reduce the overall inductor boost amplitude and/or reduce the EMI filter size. In addition, the rms current (ICOUT) of the high-frequency output capacitor of the interleaved PFC pre-regulator is less than 50% of the former compared to the single-stage topology. The reduction in the RMS current of the high-frequency boost capacitor can reduce the number of boost capacitors by up to 25%. Do not confuse the number of boost capacitors with the number of capacitors required for design. The amount of capacitor required by the converter is typically determined by the hold time.



Figure 1: The interleaved PFC boost pre-regulator consists of only two PFC boost converters.

Interleaved PFC pre-regulators reduce the total inductor energy required by the design by up to 50% compared to single-stage pre-regulators. To elaborate on this, consider the equation for the inductor energy (ES(L)) required for a single-stage PFC and the total inductor energy (EI(L1+L2)) required for the interleaved PFC. For the same power stage, if the same inductance value is used in both designs, the total inductor energy required for the interleaved design is only half that of a single-stage design. In fact, the reduced inductance energy of the staggered design can reduce the magnet volume by up to 32%.

By comparing the conduction loss (PCS) of a single-stage PFC with the overall conduction loss (PCI) of an interleaved PFC, it can be seen that an interleaved PFC pre-regulator can reduce conduction losses at most compared to a single-stage power factor correction converter. 50%. A reduction in conduction losses will result in a higher efficiency of the interleaved PFC pre-regulator at higher voltages (where conduction losses are the main losses).



In the past, power supply design engineers were forced to use discrete circuit control schemes to control interleaved PFC pre-regulators. To help power supply designers achieve interleaved design, TI introduced two interleaved PFC controllers, in which the UCC28060 controller not only allows two transfer mode PFC pre-regulators to be interleaved, but also uses constant on-time control technology. The current needs to be detected. This technique eliminates the need for a current sense resistor at the source of the boost FET, which is only required in the peak current limit circuit that protects the boost FET. The peak current limit comparator is designed to be triggered at 200 mV, which is less than 1/6 of the voltage of the current sense signal normally required by the transfer mode PFC controller. Thanks to the current sensing function, this innovative technology greatly reduces conduction losses. Figure 2 is a schematic diagram of an interleaved PFC pre-regulator using the UCC28060 control IC.


Figure 2: Schematic diagram of an interleaved PFC pre-regulator using the UCC28060 control IC.